Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform a specified logic design. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles may include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a logic design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual configuration memory cells then determine the logic design implemented by the FPGA.
Synthesis tools and place and route tools generate the configuration data from a specification of a logic design. The FPGA implements the logic design when the configuration memory cells are programmed by loading the stream of configuration data into the FPGA.
Designers rely on the tools to generate correct configuration data. However, it may be time consuming and expensive for tool makers to verify that the tools correctly generate the configuration data. Verification of the configuration data requires simulation of the loading of the configuration data into the configuration memory cells of the FPGA. A simulation of the loading of configuration data is time consuming because a large number of clock cycles is required for loading the configuration data into the FPGA. Furthermore, once the configuration data is loaded into the FPGA, it may be difficult to determine whether the configuration memory cells have the correct values.
The present invention may address one or more of the above issues.